1. Field of the Invention
The disclosure relates generally to transistor devices and, more specifically, to a method and apparatus for hardening latches.
2. Description of the Related Art
Complementary Metal-Oxide-Semiconductor (CMOS) circuits are susceptible to high-energy particles. Upon a CMOS device, such as an Silicon-On-Insulator (SOI) transistor, being biased in the OFF state and a high-energy particle, e.g., an alpha particle, being incident in the device channel or body region, the high-energy particle can generate a large number of electron-hole pairs, causing a large transient current to flow between the source and the drain. This large transient current causes a device, which is biased in the OFF (or non-conducting state) to become momentarily conducting, and this conduction can momentary turn the transistor ON, which can cause an error to occur in the CMOS circuit. This is often called a soft-error or Single-Event Upset (SEU). These types of soft errors are a major reliability concern in modern circuits. Unless storage elements are protected, soft errors can cause unrecoverable loss of data and system crashes. Various sources of high energy particles, which lead to soft errors, include impurities in packaging materials, impurities present in back of the line interconnect, and cosmic rays.
FIG. 1 illustrates a conventional latch 100. The logic states of “clock” and “clock_not” are opposite of each other. Upon “clock”=1, Field Effect Transistors (FETs) 101, 102 are ON while FETs 104/105 are OFF. The latch 100 is written such that “true”←“data.” Upon “clock”=0, FETs 101, 102 are OFF while FETs 104, 105 are ON. The latch 100 maintains its state via a pair of cross-coupled inverters formed by FETs 107, 108 and FETs 103, 106. The inverter formed by FETs 109, 110 drives external circuits. Assuming an initial state of “true”=0, FET 108 is OFF and FET 107 is ON while “comp”=1. The “comp”=1 drives FET 106 to ON and FET 103 to OFF.
Upon a high energy particle hitting, for example, the body of FET 108, which is in the OFF state, the higher energy particle raises the drain to source current such that FET 108 turns ON and node “comp” is pulled low to 0. The inverter formed by FETs 103, 106 reacts and drives its output node of “true” to a high value and the prior 0 state of node “true” is lost. Thus, the result from the impact of high energy particle is a loss of stored data.
Many different techniques have been employed to harden these circuits against soft errors. Techniques to address these soft errors include physically shielding the entire device from radiation. Logical techniques have also been employed to address SEU. For example, at a register level, parity bits are added to stored data and error correction codes are used to check for corrupted data. At the latch level, in which only a single bit of information is stored, three latches can be used to represent the same data and a 1 out of 3 majority circuit is used to read the data (i.e., ab+ac+bc). At the transistor level, redundant transistors/storage nodes may be employed and compared against one another. These techniques, however, can be expensive, in area on a chip, delay and/or power consumption, to employ. There is, therefore, a need for an improved circuit design that reduces SEU while subjecting the design to reduced overhead in area, delay, and power consumption.